1. Technical Field
The present invention relates in general to data processing, and in particular, to a multi-threaded processor and data processing system having a multi-level register file for operand storage.
2. Description of the Related Art
The architected state of a hardware thread of a processor can be defined as the information that is required by a given processor architecture for the hardware thread to achieve an architecturally defined correct result from a current point of execution. In general, the architected state of a thread is defined by volatile data within the processor, such as the contents of various user level and supervisor level registers of the processor.
As the number of simultaneous hardware threads supported by processors has increased, the size of the register sets in the processors has also increased to provide storage for the architected state of each simultaneous hardware thread. Other factors, such as an increase in the size of data words (e.g., from 32 bits to 64 bits), have also increased the size of register sets. Because the access latency and power consumption of a given set of storage locations generally increases as the size of that set of storage locations grows, the increase in the size of register sets has become a performance concern in processor design.
The concern with the access latency and power consumption of register sets in processors has led to the introduction of a number of architectural developments in processors. For example, some architectures have introduced mirrored sets of certain architected registers that may be independently accessed. In addition, other architectures have adopted multi-level register files in an attempt to reduce the size of at least one level of register storage. While such developments have been generally provided benefits, these developments have not heretofore provided a solution that scales well with the number of simultaneous hardware threads.